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L9341
QUAD LOW SIDE DRIVER
AVANCE DATA
DU/DT AND DI/DT CONTROL PWM CONTROLLED OUTPUT CURRENT SHORT CURRENT PROTECTION AND DIAGNOSTIC INTEGRATED FLYBACK DIODE UNDERVOLTAGE SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DIAGNOSTIC OVERTEMPERATURE DIAGNOSTIC
MULTIPOWER BCD TECHNOLOGY
Multiwatt 15 ORDERING NUMBERS: L9341V L9341H
DESCRIPTION The L9341 is a monolithic integrated circuit realized in Multipower BCD-II mixed technology. The driver is intended for inductive loads in synchronous PWM applications, especially for valve drivBLOCK & APPLICATION DIAGRAM
ers. The output voltage and current rise and fall slopes du/dt and di/dt are controlled.
V s
Is VS 7 C BAT D BAT
220nF
Vcc I cc 10uF
VCC 4
COMP1
UNDERVOLTAGE SHUTDOWN
DIAGNOSTIC COMP2
V
flyth
V offth
OUT1 2 I OUT1
THERMAL FLAG di / dt & du / dt CONTROL
I outs REXT 12 10nF DRIVER C
10nF O1
SHORT CURRENT PROTECTION
R ext 12.4k RES1 9 BIAS 10 CHANNEL 1
RES2
SERIAL INTERFACE &
OUT2 CHANNEL 2 1 I C OUT2
CS 3 SCLK 11 SDI 5 SDO 13 OSC 6
PWM CONTROLL
O2 10nF
OUT3 CHANNEL 3 15 I C OUT3
O3 10nF
OUT4 CHANNEL 4 14 IOUT4 C 8 O4 10nF
C
OSC
GND I GND
March 1994
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L9341
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VS Vspmax Vst Vin Vout VCC Voltage Range VS Voltage Range VS Voltage Range for t 400ms Schaffner Transient Pulses on VS Input Voltage Range for SDI; SCLK;CS;RES1;RES2 Output Voltage Range for all Outputs: Negative Positive Output Current for all Outputs: Negative Positive for Transient with t < 10ms Negative Positive Schaffner Transient Pulses on Output VESD ESD Voltage Capability (MIL 883 C) Parameter Value -0.3 to 6 -0.3 to 24 -2 to 40 see note 1 -0.3to VCC+0.3 - 0.3 intern. clamped to VS -2 +2 -5 5 see note 2 1500 V V V A A A A Unit V V V V
Iout
THERMAL DATA
Symbol Rth j-case Rth j-amb Tsdh Tsd Parameter Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient mounted on PC Board Thermal Hysteresis Thermal Diagnostic Value 3 35 20 Tj > 150 Unit C/W C/W C C
Notes: 1. Schaffner transient specification: DIN 40839 test waveforms of the following type: 1, 2, 3a, 3b, 5 and 6. The pulses are applied to the application circuit according to fig. 3. 2. The maximum output current results from the Schaffner pulses specified in note 1.
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L9341
ELECTRICAL CHARACTERISTICS (Unless otherwise specified: 8V VS 24V; 4.7V VCC 5.3V; - 40 C Tj 150C; IO 1A (note 3); IO 1.5A; Vsp = VS for t 400ms; VOUTP = VOUT for t 400ms; Rext = 12.4K 1%).
Symbol Iccq Isq Vccu Vcc r Ron Io off Parameter Vcc Quiescent Current Vs Quiescent Current Vcc Undervoltage Threshold Vcc Range for RES1 and RES2 Operation On Resistance Off State Output Current Io = 1A Tj = 125C Tj = 25C 1 1 2.5 Test Condition All Outputs Off All Outputs Off See Note 4 3 3 750 450 4 10 Vs +1.3 Vs +1.1 17 20 0.7*Vcc - 0.3 0.3 RES i = H; -2V Vsp 8V RES i = H; 8V Vsp 40V - 2V Vsp 40V ISDO = -1mA -2V Vsp 40V ISDO = 1mA -2V Vsp 40V 0 VSDO Vcc - 2V Vsp 40V See Note 6 40 Vsp 8V Vs 8V - 10 5 - 10 0.9*Vcc 0 - 10 1/16 0.93*Kfn Vs - 1 1.5 1.5 see Note 7 (from 10 to 90% of Vo) Fig. 2 0.1 Io 1.5A (from 10 to 90% of Io) 1.5 5 1.0 25 Kfn 44 52 500 Vcc +0.3 0.3*Vcc 1 10 10 10 Vcc 0.4 10 15/16 1.07*Kfn Vs - 0.4 2 2.5 15 10 125 V V V A s V/s mA/s Min. Typ. 1 14 4 Max. 3 25 4.7 Unit mA mA V V m m mA mA V V mA mA A V V V A A A V V A
Outputs Off 1.4V Vo Vs Voutp = Vsp = 40V Io = 1A Output Off Tj = 25C Tj = 125C Io = 1A Output Off Vs = 24V Vsp = 40V Vsp - Vo = 40V
Voutf
Output Voltage During Flyback
Igndf
Current to GND during Flyback (see note 5) Reverse Leakage Current High Input Level of SCLK, SDI, CS, RES1, RES2 Low Input Level of SCLK, SDI, CS, RES1, RES2 Hysteresis of Reset Inputs RES1, RES2 Input Current on RES1,RES2 Input Current on SCLK,SDI,CS High Level SDO Output Voltage Low Level SDO Output Voltage SDO Tristate High-Z Leakage Current PWM Duty Cycle Frequency Accuracy Constant Flyback Diagnostic Comparator Threshold Off State Diagnostic Comparator Threshold Output Current Limitation Threshold Delay Time PWM Signal to Out. Output Voltage Rise and Fall Slope | du/dt | Output Current Rise and Fall Slope |di/dt|
Iout r VinH VinL VREShys IinRESH Iin VSDOH VSDOL ISDOZ PWMduty Kf Vflyth Voffth Ioutl tdpo Sov Soc
Notes:
1T Io (t) dt ; T0 4. The outputs are switced off for Vcc Vccu. The logic is not reseted. For a reset, RES1 or RES2 must be used. 5. This current is measured in the GND - terminal when one single output is in flyback and consists of the supply current added to the value of the output current source and the leakage current of the flyback diode. This leakage current is less than 1% of the nominal flyback current. fosc Kf with fosc = 6. The PWM frequency is defined by an external capacitor. The PWM oscillator frequency is: fpwm = 1A/V and kin = 15 10-6; 32 Cosc the range is: 300Hz fpwm 3000Hz. The OSC Pin can be alternatively driven by an external TTL / CMOS signal. 7. For Iout Ioutl an internal comparator switches the corresponding output off for the current PWM cycle. 3. The mean value is Io =
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L9341
Figure 1: Logic Diagram of PWM Generation.
INTERNAL CLOCK
CLK
15 PWM1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWM2
PWM3 PWM4
Figure 2: Output Switching Diagram.
+12V
Is Vs
D If ID OUT I out Current through Low Side Switch t dpo ID 5% 220 nF Internal PWM Signal 5 20 mH Output Voltage V t dpo out 12V f
du/dt
5%
du/dt
0 1A
DMOS
10 nF V out GND
di/dt
di/dt
0 1A
Current through
Is
Flyback Diode
I
f
di/dt
di/dt
0
Figure 3: Test Circuit for Schaffner Pulses.
+12V
220 nF D1 -2V to 40 V
Schaffner
Vs VCC
Generator
OUT1 OUT2 OUT3 OUT4
+5V
10 uF
GND
4 x 1 nF
4 x 10 nF
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L9341
Figure 4: Synchronous Serial Interface Protocol.
CS SCLK SDI SDO MSB MSB 14 14 13 13 12 12 11 11 3 3 2 2 1 1 LSB LSB
CS
tclcl t chcl
t ch tcl t su th t clch t chch
SCLK SDI
t clz td
15
t oh
0
t zch
SDO
15
14
0
fclock tch tcl tcicl tchcl tclch tchch tciz tzch tsu th td toh
Clock Frequency Width of Clock Input High Puls Widh of Clock Input Low Puls Clock Low Before CS Low Clock High After CS Low Clock Low Before CS High Clock High After CS High SDO Low-Z CS Low SDO High-Z CS High SDI Input Setup Time SDI Input Hold Time SDO Output Delay Time (CL = 50pF) SDO Output Hold Time
min. DC min. 200ns min. 200ns min. 200ns min. 200ns min. 200ns min. 200ns min. 0ns min. 80ns min. 80ns
max. 2MHz
max. 400ns max. 400ns
max. 100ns min. 0ns
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L9341
Figure 5: PWM Generation Function Table.
Bit 3 - 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM1 15/16 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 PWM2 15/16 15/16 14/16 13/16 12/16 11/16 10/16 9/16 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 PWM3 15/16 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 PWM4 15/16 15/16 14/16 13/16 12/16 11/16 10/16 9/16 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 OUTPUT OFF ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON
Figure 6: PWM Information From Microcontroller to QLSD.
Bit. Nr. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40 P41 P42 P43 Contents PWM Duty Cycle for Channel 1 / Bit 0: LSB PWM Duty Cycle for Channel 1 / Bit 1 PWM Duty Cycle for Channel 1 / Bit 2 PWM Duty Cycle for Channel 1 / Bit 3 : MSB PWM Duty Cycle for Channel 2 / Bit 0 : LSB PWM Duty Cycle for Channel 2 / Bit 1 : PWM Duty Cycle for Channel 2 / Bit 2 : PWM Duty Cycle for Channel 2 / Bit 3 : MSB PWM Duty Cycle for Channel 3 / Bit 0 : LSB PWM Duty Cycle for Channel 3 / Bit 1 : PWM Duty Cycle for Channel 3 / Bit 2 : PWM Duty Cycle for Channel 3 / Bit 3 : MSB PWM Duty Cycle for Channel 4 / Bit 0 : LSB PWM Duty Cycle for Channel 4 / Bit 1: PWM Duty Cycle for Channel 4 / Bit 2 : PWM Duty Cycle for Channel 4 / Bit 3 : MSB
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L9341
Figure 7: Diagnostic Information from QLSD to Microcontroller.
Bit Nr. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name F11 F12 F21 F22 F31 F32 F41 F42 RES1 RES2 TSDF C1 C2 C3 C4 1 Contents COMP1 State at Positive Edge of PWM1 (0: Vout1 > Vflyth; 1: Vout1 < Vflyth) COMP2 State at Negative Edge of PWM1 (1: Vout1 > Voff th; 0 : Vout1 < Vofth) COMP1 State at Positive Edge of PWM2 (0: Vout2 > Vflyth; 1: Vout2 < Vflyth) COMP2 State at Negative Edge of PWM2 (1: Vout2 > Voft h; 0 : Vout2 < Vofth) COMP1 State at Positive Edge of PWM3 (0: Vout3 > Vflyth; 1: Vout3 < Vflyth) COMP2 State at Negative Edge of PWM3 (1: Vout3 > Voff th; 0 : Vout3 < Vofth) COMP1 State at Positive Edge of PWM4 (0: Vout4 > Vflyth; 1: Vout4 < Vflyth) COMP2 State at Negative Edge of PWM4 (1: Vout4 > Voffth; 0 : Vout4 < Vofth) Logic State of RES1 Input (0: RES1 = L ; 1: RES1 = H) Logic State of RES2 Input (0: RES2 = L ; 1: RES2 = H) Thermal Diagnostic Flag ( 0: Overtemperature ; 1:Normal ) Current at Negative Edge of PWM1 ( 0: Iout > Ioutl ; 1: Iout < Ioutl) Current at Negative Edge of PWM2 ( 0: Iout > Ioutl ; 1: Iout < Ioutl) Current at Negative Edge of PWM3 ( 0: Iout > Ioutl ; 1: Iout < Ioutl) Current at Negative Edge of PWM4 ( 0: Iout > Ioutl ; 1: Iout < Ioutl) Framing Information (always 1)
Figure 8.
PWM
PWM
ID
V OUT
tC
V OUT
t dPO tV t t
t dPO
tV PWMOFF min
PWMON min
Sample point COMP2 Sample point COMP1
Sample point COMP1 Sample point COMP2
Fig.1 Fig. A
Note: For safty diagnostic take notice of the following conditions: tPWMON tdPOMAX + tC + tV (see Fig. A) tPWMOFF tdPOMAX + tV (see Fig. B) tC = ID SOCMIN tV = Voutfmax SOVMIN
Fig.2 Fig. B
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L9341
FUNCTIONAL DESCRIPTION The U511 is a PWM quad low side driver for inductive loads. The duty cycle of the internal generated PWM signal is set by a microcontroller via a serial interface for each output. An output slope limitation for both dv/dt and di /dt is implemented to reduce RFI. The PWM generation is realized avoiding a simultaneous output switching. As a result, di/dt becomes smaller. Integrated flyback diodes clamp the output voltage during the flyback phase of the low side switches. The driver is protected against short circuit. An undervoltage shutdown circuit switches off all outputs if Vcc is less then Vccu. Below the shutdown voltage all outputs remain in off state regardless of the input state. After each malfunction which resets the driver, only the serial link interface can reactivate the normal function. In case of overcurrent (Iout = I out1), an internal comparator switches the output off. The overcurrent information can be read via the serial link for each driver separately at the negative edge of the corresponding PWM signal. The interface to the microcontroller is realized with a 16 bit synchronous serial peripheral interface (SPI). If CS is switched low, the serial link becomes active and SDO goes to low impedance. At the rising edge of the SCLK signal, one of the 16 bit of data stored in a shift register appear sequencely at SDO. These data contain the 8 error flags, the status of thermal diagnostic flag and the external reset sources RES1, RES2 and the overcurrent flgs c1...c4. The last bit is framing information (see fig. 7). At each falling edge of SCLK, one of the 16 bits of data sent by the microcontroller is transferred via the SDI input to the driver. These data contain the duty-cycle information for the internal PWM generation (4 times 4 bit). On the rising edge of CS the previously stored information is transferred to the circuits. SDO become now high impedance and SDI is inactive. The serial interface of the QLSD is cascadable with the serial link interface of another QLSD, thus obtaining a 32 bit serial link information wich can control eight inductive loads. For a safety data transfer the takeover of data bits is only realized when the number of SCLK - clocks is n x 16 (n 1). The PWM duty cycle is set by 4 bit for each output independently via the serial link. If all four bits for an output are zero, the output is turned off, but the error diagnosis will work correctly (see fig. 5 and 6). The PWM frequency is defined by an external capacitor on the OSC pin. Rext defines through the reference current the output current slope, the diagnostic current sink and the internal oscillator frequency (together with Cosc). For error diagnosis the voltage on the output is measured during the on and off state of the particular output driver. Upon the rising edge of the PWM signal (at this moment the power output is off and will be switched on) the status of COMP1 is stored into an internal latch. On the falling edge of the PWM signal ( the power output is on and will be switched off) the status of COMP2 is stored into another internal latch. This information can be read via the serial link for each output driver separately (see fig. 7). The thermal diagnostic switch the thermal flag to 0 in case of overtemperature T Tsd. It will be switched to 1 with the hysteresis Tsdth in case of T < Tsd - Tsdh. To avoid male functions due to extensive noise or spikes at the supply pins VCC, VS and Rext must be blocked externally via capacitors.
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L9341
MULTIWATT15 PACKAGE MECHANICAL DATA
DIM. MIN. A B C D E F G G1 H1 H2 L L1 L2 L3 L4 L7 M M1 S S1 Dia1 21.9 21.7 17.65 17.25 10.3 2.65 4.25 4.63 1.9 1.9 3.65 4.55 5.08 17.5 10.7 22.2 22.1 0.49 0.66 1.02 17.53 19.6 20.2 22.5 22.5 18.1 17.75 10.9 2.9 4.85 5.53 2.6 2.6 3.85 0.862 0.854 0.695 0.679 0.406 0.104 0.167 0.182 0.075 0.075 0.144 0.179 0.200 0.689 0.421 0.874 0.870 1.27 17.78 1 0.55 0.75 1.52 18.03 0.019 0.026 0.040 0.690 0.772 0.795 0.886 0.886 0.713 0.699 0.429 0.114 0.191 0.218 0.102 0.102 0.152 0.050 0.700 mm TYP. MAX. 5 2.65 1.6 0.039 0.022 0.030 0.060 0.710 MIN. inch TYP. MAX. 0.197 0.104 0.063
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L9341
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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